Intel has made some main modifications and bulletins regarding upcoming merchandise and the way future enhancements to the corporate’s manufacturing will likely be communicated. These modifications may have a big affect on how we speak about Intel merchandise going ahead.
A long time in the past, there was an trade group accountable for defining the traits of every new lithography node and an agreed-upon conference for what a brand new node meant. The precise apply of naming a node in nanometers — 45nm, 32nm, 28nm, and so forth — has been divorced from any goal metric for a few years now. Right this moment, TSMC, Intel, and Samsung all have totally different requirements for what a given “node” is. TSMC’s 16nm FinFET course of retained lots of the similar dimensions as its 20nm node, however added FinFET. 12nm was then an extra refinement of 16nm, but it surely didn’t supply the density enchancment that the numerical discount from 20nm to 12nm would indicate. These variations between firms are why we’ve got usually written that Intel’s 14nm was extra similar to TSMC’s 10nm, and its 10nm extra similar to TSMC’s 7nm.
Intel’s new methodology for speaking node enhancements acknowledges this reality. The corporate will drop the “nm” from future nodes and discuss with them by quantity alone — Intel 7, Intel four, and so forth down the road. The “A” stands for “angstrom”, the unit of measurement under nanometer. One angstrom = 100 picometers, whereas one nanometer = 1000 picometers.
Earlier nodes will nonetheless be referred to by their unique nomenclature. Tiger Lake continues to be thought-about to be constructed on Intel’s 10nm course of. When Alder Lake launches, nonetheless, its “Enhanced SuperFin” gained’t be labeled as 10nm++ or +++ or what have you ever — it’ll be constructed on Intel 7. Intel 7nm, when it arrives, will likely be referred to as Intel four. It’s not clear whether or not Intel three represents a refined 7nm node or 5nm, however refined 7nm appears extra possible. Intel’s 7nm is anticipated to pattern in 2022 and ship for quantity in 2023, and the “breakthrough” of Intel 20A is anticipated in H1 2024. This will likely counsel a two-tier strategy the place Intel three is a refined and polished model of Intel four, however not a brand new node. Intel may also introduce 20A for cell first whereas holding desktop chips again on the older node, because it’s carried out since Broadwell debuted in 2014.
Renaming the nodes to a dimensionless quantity is ok by us. Metrics like “7nm” are basically dimensionless already. Appending “nm” to the again of the quantity as if there’s a relationship between the node title and the metric is complicated and encourages individuals to consider such a relationship exists.
In accordance with Intel, its new node names are primarily based on relative enhancements to performance-per-watt, not uncooked efficiency. At current, node names usually are not clearly anchored to any single metric of enchancment (efficiency, energy, or space). New nodes have at all times been events for foundries to tout their manufacturing prowess, however the particular enhancements of a node transition are specific to itself. The massive hole between 28nm and 20nm would appear to indicate that the latter could be a serious node, however comparatively few firms used it. TSMC’s 16nm FinFET (which used the identical BEOL as 20nm) was the key node. AMD’s shift from 32nm SOI to 28nm planar silicon at GF didn’t have a big internet affect on energy consumption, despite the fact that the node quantity fell by four. TSMC’s 5nm provides modest efficiency and energy consumption advances over its 7nm node, but it surely’s as much as 1.8x extra dense, in comparison with energy and efficiency positive aspects within the 1.15x – 1.2x vary. I’ve written previously that new nodes are outlined by no matter chum bucket of expertise engineers can dump in to make issues work higher after node shrinks make the whole lot worse, and it will proceed to be true.
This slide additionally reiterates that Intel will introduce EUV at 7nm four and lengthen its utilization at three. At 20A, Intel will introduce ribbonFETs. These are its model of the nanowires and nanosheet expertise at present being researched at TSMC and Samsung. Intel three would be the firm’s final iteration of FinFET, and Intel desires to be able of “unquestioned management” by 2025. Intel four will likely be a full node die shrink from Intel 7.
PowerVia is Intel’s new expertise for energy supply. As a substitute of operating interconnects on high of the transistor stack, all such circuitry will transfer to the underside. In accordance with Intel, this permits the highest of the chip for use for sign routing, eliminates voltage droop (with a corresponding enchancment in energy effectivity), and would enable the corporate to make use of both denser sign routing in complete or quicker wire speeds. Wire pace is a serious supply of delay in trendy chip designs, so enhancements listed here are very helpful.
Past PowerVias, Intel is engaged on two new 3D interconnect applied sciences: Foveros Omni and Foveros Direct. Foveros Omni options copper columns to maneuver energy to the highest die of the Foveros stack, minimizing the TSV penalty for this sort of bonding. Foveros Omni can even allow Intel to mix totally different base nodes constructed on totally different manufacturing processes collectively and provides 25-micron solder bumps. Foveros Direct permits for direct copper-copper bonds with 10-micron bumps, boosting general density. Intel has not revealed if EMIB, its 2.5D bridge interconnect, will proceed to evolve.
Intel will introduce 12 layers of EUV at Intel four and an unknown for Intel three and Intel 20A. Intel has not ordered as many EUV machines as a few of its opponents, but it surely expects to deploy high-NA EUV machines sooner or later. Excessive-NA EUV is an alternative choice to multi-patterned EUV, and it’s potential Intel intends to make bigger EUV purchases when high-NA machines are lastly out there.
Intel Doubles Down on Manufacturing Prowess
Intel is emphasizing its historic manufacturing chops with these bulletins. It’s just like what the corporate did again in 2018 for its Tech Day, with the caveat that late 2021/early 2022 would be the first time we see among the applied sciences Intel introduced then, like Foveros, in transport hardware.
Intel’s implicit argument to potential foundry prospects and end-users alike is that its 10nm troubles represented a deviation from many years of wonderful execution, not a brand new regular for the corporate. During the last 30 years, Intel has led the semiconductor trade for for much longer than it has lagged it. Appointing a longtime Intel insider like Pat Gelsinger was a part of Intel’s technique to color itself as returning to its roots.
However Intel isn’t simply aiming for a return to its glory days. The corporate advised us that superior nodes, explicitly together with Intel three and Intel 20A, will likely be provided to its foundry prospects. The implication is that applied sciences like Foveros, Foveros Omni, Foveros Direct, and PowerVias will likely be as effectively. Intel desires its prospects to affiliate it with manufacturing excellence, whether or not the silicon inside a given gadget is x86-based or not. So as to make that occur, it’ll want to supply aggressive options towards rival TSMC.
Final month, I wrote a deep dive into the query of whether or not comparisons between so-called “CISC” and “RISC” CPUs are an efficient strategy to evaluate trendy microprocessors. Again within the mid-1990s to early 2000s, Intel’s superior manufacturing was key to its long-term success and x86’s eventual takeover of the CPU market. TSMC and Samsung are rather more succesful than any RISC CPU producer was in that period, whereas Intel is in a weaker relative place, however the firm’s launch roadmap is aggressive.
As scaling turns into harder, absolutely the contribution of lithography to every node’s efficiency, energy, and space enhancements has already begun to drop. Intel’s choice to emphasise different interconnect applied sciences alongside an eventual shift to ribbonFETs acknowledges this pattern. We don’t understand how Foveros, Foveros Omni, or Foveros Direct will evaluate with choices from TSMC, however any benefits Intel can wring from its new interconnect strategies can be utilized to decrease general x86 energy consumption, enhance efficiency, or each.
Oh, one final tidbit: Intel’s Meteor Lake taped in this quarter. Tape-in means the assorted design teams contributing IP blocks to Meteor Lake have submitted their work to the ultimate product database. That is distinct from tape-out, which refers to sending a accomplished design to the manufacturing facility for manufacturing. Meteor Lake is anticipated to launch in 2023, so we’re nonetheless just a few years from business quantity.